1. Field of the Invention
The present invention relates to computer bus protocols and more particularly to computer bus protocols for performing direct memory access (DMA) transactions.
2. Description of Related Art
Cost reductions of computer systems can often be realized by simplifying the interconnections between computer system components. Thus, signaling protocols which allow computer components to communicate using fewer dedicated signal lines can often reduce the expense of computer system manufacture. In fact, the allocation of component interconnects is often very closely controlled due to the high cost of each interconnect both at the component level and at the system level.
Improving performance, in contrast, often requires more signal lines to improve information throughput between devices. Thus, cost savings and performance improvements typically need to be balanced. Specific knowledge of signaling protocols or component functions may be used in some cases to allow computer system interconnections (e.g., component pins or other connectors and signal lines) to be used for multiple functions through the use of multiplexing.
One function found in many computer systems is direct memory access (DMA) data transfer. A DMA transfer allows blocks of information to be exchanged between a system device and a system memory without unnecessarily tying up the resources of the system processor. While the processor initiates DMA transfers, a DMA controller actually manages DMA transfers, allowing the processor to perform other tasks.
As shown in FIG. 1a, systems employing a common bus architecture such as the Industry Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA) expansion bus structures typically have a series of DMA request (DREQ1-DREQn#) and DMA acknowledge (DACK1-DACKn#) signal lines connecting DMA agents to DMA controllers. A DMA agent is any bus agent which is capable of performing a DMA transaction. Such an agent may also be capable of performing other operations which do not involve DMA access, and which may in fact use entirely different protocols. A DMA controller typically includes logic to provide the DMA agent access to the system and may include logic to arbitrate between multiple DMA agents if such agents are present.
The DREQ and DACK signal lines are individually routed between DMA agents 110a-110n and a DMA controller 100. The DMA controller 100 is typically coupled through a host bus 115 to a bus bridge 120, a memory 130, and a processor 125. Many such systems accommodate up to seven DMA agents, requiring up to seven pairs of request and acknowledge signal lines.
While minimizing the interconnections between computer components reduces costs, simplified connectivity may also be useful in other ways. For example, having fewer signal lines can lead to reduced signal propagation delays if signal line layout can be improved. Additionally, simpler connectors may improve durability or ease of connection where certain components or subsystems are not permanently affixed, but rather may be frequently or infrequently detached or disconnected.
One common example is a docking station which allows a mobile computing device to mate with a more stationary computing device. The stationary device may include additional or larger peripheral devices such as a disk drive, a network connection, keyboard, mouse, monitor, or other devices which may be inconvenient to routinely transport. Typically, such a docking arrangement includes a set of connectors on a surface of the mobile computing device (e.g., the back of a laptop computer) which interfaces with a mating set of connectors in the receiving device.
In order to reduce the number of connectors necessary to conduct DMA accesses through a computer host bus such as the Peripheral Component Interconnect (PCI) bus, DMA request and acknowledge signals have been serially encoded using the PCI bus request (REQ#) and grant (GNT#) signal. Such an arrangement allows a DMA request on a secondary bus to be transmitted over the PCI bus using the standard REQ# and GNT# signal lines. Additionally, this technique allows a DMA controller located in a separate computing device to obtain bus access from the central system I/O controller using PCI request and grant signals.
One such prior art system is illustrated in FIG. 1b. This system includes a DMA channel number encoder/decoder 105 coupled through a host bus 115 to a bus bridge 120, a memory 130, and a processor 125. The DMA channel number encoder/decoder 105 handles DMA requests signaled by DMA agents 110a-110n to the DMA controller 100 using DREQ1#-DREQn# signals and acknowledged by the controller using DACK1#-DACKn# signals. The DMA channel number encoder/decoder 105, however, does not directly place these DMA transactions on the host bus 115, but rather conveys the requests by serially signaling the DMA channel number or numbers to a system I/O controller 150 using a REQ# signal line 162. The system I/O controller 150 includes a DMA controller 100 which performs arbitration between the various DMA agents requesting access to the host bus 115.
A second DMA controller 160 may signal DMA requests to the system I/O controller 150 in a similar fashion. This second DMA controller 160 may be located in a portable computing device and coupled to the host bus 115 via a bus bridge or other connector. Such an arrangement allows DMA requests to be conveyed from the N DMA agents 170a-170n in a separate device to the system I/O controller 150 using the REQ# and GNT# lines of the DMA controller 160. Further details of related systems are described in U.S. patent application Ser. No. 08/426,818 entitled "Direct Memory Access Transfer Protocol," and U.S. patent application Ser. No. 08/426,825 entitled "A Method and Apparatus for Handling Bus Master Channel and Direct Memory Access (DMA) channel Access Requests at an I/O Controller."
While this approach channels a number of DMA requests from separate DMA agents through a single request/grant pair, such systems do not alter or optimize the expansion bus DMA signaling protocol. Instead, such systems continue using dedicated request/acknowledge and request/grant signal line pairs to convey DMA requests on the expansion bus.
One additional prior art DMA signaling protocol utilizes two address lines to signal information regarding a particular DMA transfer. In such a system, two address lines (e.g., AO and Al) indicate which byte(s) of the data bus are used to transfer data. This prior art system does not, however, eliminate or reduce the overhead of transmitting request and acknowledge signals for DMA transfers.
Thus, while DMA signaling protocols have evolved, prior art approaches still require an unnecessarily large number of signal lines to effectuate DMA transfers. Any reduction in the number of signal lines required may generally reduce the cost of computer systems and may also ease connection and reduce physical wear for computer components which may be connected to or either internally or externally disconnected from a computer system.